Dynamic branch prediction and control speculation
نویسندگان
چکیده
Branch prediction schemes have become an integral part of today’s superscalar processors. They are one of the key issues in enhancing the performance of processors. Pipeline stalls due to conditional branches are one of the most significant impediments to realise the performance potential of superscalar processors. Many schemes for branch prediction, that can effectively and accurately predict the outcome of branch instructions have been proposed. In this paper, an overview of some dynamic branch prediction schemes for superscalar processors are presented.
منابع مشابه
Control Flow Speculation in Multiscalar Processors
The Multiscalar architecture executes a single sequential program following multiple flows of control. In the Multiscalar hardware, a global sequencer, with help from the compiler, takes large steps through the program’s control flow graph (CFG) speculatively, starting a new thread of control (task) at each step. This is inter-task control flow speculation. Within a task, traditional control fl...
متن کاملHierarchical Control Prediction: Support for Aggressive Predication
Predication of control edges has the potential advantages of improving fetch bandwidth and reducing branch mispredictions. However, heavily predicated code in out-of-order processors can lose significant performance by deferring resolution of the predicates until they are executed, whereas in nonpredicated code those control arcs would have remained as branches, and would be resolved immediatel...
متن کاملImproving Branch Predictability in Java Processing
Java programs are becoming increasingly prevalent on numerous platforms ranging from embedded systems to enterprise servers. Dynamic translation (interpretation and compilation), frequent calls to native interface libraries or OS kernel services and abundant usage of virtual methods by Java programs can complicate the intrinsic predictability of the control flow that can be exploited by an ILP ...
متن کاملUnderstanding the Backward Slices of Performance Degrading Instructions Craig
For many applications, branch mispredictions and cache misses limit a processor's performance to a level well below its peak instruction throughput. A small fraction of static instructions, whose behavior cannot be anticipated using current branch predictors and caches, contribute a large fraction of such performance degrading events. This paper analyzes the dynamic instruction stream leading u...
متن کاملTraveling Speculations: An Integrated Prediction Strategy for Wide-Issue Microprocessors
Performing multiple, accurate, low-latency predictions is crucial to improving instruction throughput in future wide-issue microprocessors. However, demands of wide-issue processing coupled with implementation challenges posed by high clock frequencies present obstacles to these prediction goals. This paper proposes the Traveling Speculation framework to accommodate predictions in a wide-issue ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
- IJHPSA
دوره 1 شماره
صفحات -
تاریخ انتشار 2007